The invention relates in general to non-volatile memory devices, and, more particularly, to a non-volatile memory device and a method of manufacturing the same wherein the program speed can be enhanced and interference phenomena can be reduced.
A non-volatile memory device is a device that stores and reads information according to the movement of the threshold voltage in a state where electrons are injected into the floating gate and a state where electrons are not injected into the floating gate.
The program speed of the non-volatile memory device is greatly influenced by the coupling ratio (i.e., an index indicating what percentage of a bias applied to the control gate is applied to the floating gate). The coupling ratio tends to be proportional to the capacitance between the control gate and the floating gate. In order to improve the program speed, an overlapping area between the control gate and the floating gate must be increased.
FIG. 1 is a cross-sectional view of a conventional non-volatile memory device.
Referring to FIG. 1, the conventional non-volatile memory device includes a semiconductor substrate 10, a floating gate 15, and a control gate 17. The semiconductor substrate 10 includes active regions defined by isolation layers 13 of a shallow trench structure. The floating gate 15 includes first polysilicon layers 12 laminated on the active regions with gate insulating layers 11 dispersed between the first polysilicon layers 12 and the semiconductor substrate 10, and second polysilicon layers 14 formed on the first polysilicon layers 12 and predetermined regions of the isolation layers 13 adjacent to the first polysilicon layers 12. The control gate 17 is formed on the floating gate 15 with a dielectric layer 16 of an ONO (oxide-nitride-oxide) structure disposed therebetween.
The non-volatile memory device described above is advantageous in improving the program speed because the size of an overlapping area between the floating gate 15 and the control gate 17 is increased due to the thickness of the second polysilicon layer 14. However, an overlapping area between floating gates adjacent in a bit line direction is increased and a distance between floating gates adjacent in a word line direction becomes smaller than a width of the isolation layer 13 due to the second polysilicon layer 14. Accordingly, the interference phenomenon is increased.
In the interference phenomenon, the threshold voltage of a reference cell is varied depending on whether neighboring cells are eased or programmed. If the interference phenomenon is increased, cell distributions are widened and the characteristic and uniformity of a device becomes difficult, resulting in read failure.